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          MIT6.S081-Lab3预备(1)-页表概述与内核地址空间
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        <h2 id="页式硬件"><a href="#页式硬件" class="headerlink" title="页式硬件"></a>页式硬件</h2><p>​    通常来说，包括RISC-V指令集都是使用虚拟地址来对内存进行虚拟化，代码或进程都不直接使用物理地址，而是使用虚拟地址，页表就是将虚拟地址映射到物理地址的桥梁。</p>
<p>XV6基于Sv39 RISC-V运行，所以64位的虚拟地址，只使用了低39位，页表逻辑上是2^27个页表条目也就是PTE组成的数组，PTE由44位的PPN也就是物理页码，还有标志位组成。</p>
<p><img src="https://i.loli.net/2021/11/01/oVtOcBXlwxyfIKS.png" alt="image-20211101115943065"></p>
<a id="more"></a>

<p>根据图，虚拟地址使用39位中的27位index来查找对应的PTE，然后再有PTE查找56位的物理地址，物理地址前44位就是PPN，低12位就是虚拟地址的Offset。</p>
<p>页表通过逻辑到物理地址的转化给了os控制权，转换细粒度是一个个对齐的页面，一个页面4096byte。</p>
<p>想要只用一个页表来映射肯定是不可能的，不然页表非常庞大，所以实际上是多级页表的映射。</p>
<p><img src="https://i.loli.net/2021/11/01/h7Ufo9DnL5lCEGv.png" alt="image-20211101120602919"></p>
<p>虚拟地址前25位留存，来定义或者扩展功能，页表实际是三级的树形结构存在物理内存里，树的root就是一个4096byte的页表，有512个PTE，每个PTE占8字节也就是64位，然后硬件用27位index中的前9位在root页表中选择PTE，中间9位在下一级页表选择PTE，最后9位在最下级页表选择PTE。</p>
<p>只要任何一个转换地址PTE不存在，就会触发异常中断。多级页表允许了页表在大范围虚拟地址没有映射的情况下只关注部分页表而不是整个大型的页表页面。</p>
<p>PTE的标志位组成如上图。代码定义kernel/riscv.h</p>
<p>硬件要使用页表，就必须把根页表的物理地址写入到satp寄存器，否则硬件根本找不到要去哪找页表来映射。多核CPU上每个CPU都有自己的satp。</p>
<h2 id="内核地址空间"><a href="#内核地址空间" class="headerlink" title="内核地址空间"></a>内核地址空间</h2><p>每个进程都会由内核维护一个页表，来描述每个进程的用户地址空间，当然内核地址空间也需要1额外一个页表来描述。内核配置地址空间布局。</p>
<p>文件(kernel/memlayout.h) 声明了内核布局常量。</p>
<p><img src="https://i.loli.net/2021/11/01/p9Nd4TFWtRHiJVq.png" alt="image-20211101123513037"></p>
<p>Qemu模拟器包括了从物理地址开始0x80000000，到0x86400000结束的物理内存，结束也就是上图的PHYSTOP，IO设备，等其他硬件接口作为内存映射控制寄存器给软件，这些控制寄存地址在0x80000000一下，内核对这些特殊物理地址写入读取来控制设备。</p>
<p>内核直接映射获取内存和内存映射设备寄存器，将资源映射到虚拟地址和物理地址相等的地址，就是内核本身在虚拟地址和物理内存地址位置都在0x80000000，上图KERNBASE处，内核的fork操作会直接把分配的物理地址作为虚拟地址。</p>
<p>上图中kernel stack与tramponline page就是间接映射，突然蹦床页面就在虚拟地址空间的顶部，用户页表也具有相同映射。内核栈页面会被映射到Guard page下，保护页PTE_V位无效，内核栈overflow就会引发内核触发panic，没guard page就会产生老生常谈的stack overflow，导致栈错误。保护页是不会占据物理地址的。内核在权限<code>PTE_R</code>和<code>PTE_X</code>下映射蹦床页面和内核文本页面。内核从这些页面读取和执行指令。内核在权限<code>PTE_R</code>和<code>PTE_W</code>下映射其他页面，这样它就可以读写那些页面中的内存。</p>
<figure class="highlight cpp"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// the kernel expects there to be RAM</span></span><br><span class="line"><span class="comment">// for use by the kernel and user pages</span></span><br><span class="line"><span class="comment">// from physical address 0x80000000 to PHYSTOP.</span></span><br><span class="line"><span class="meta">#<span class="meta-keyword">define</span> KERNBASE 0x80000000L</span></span><br><span class="line"><span class="meta">#<span class="meta-keyword">define</span> PHYSTOP (KERNBASE + 128*1024*1024)</span></span><br><span class="line"></span><br><span class="line"><span class="comment">// map the trampoline page to the highest address,</span></span><br><span class="line"><span class="comment">// in both user and kernel space.</span></span><br><span class="line"><span class="meta">#<span class="meta-keyword">define</span> TRAMPOLINE (MAXVA - PGSIZE)</span></span><br><span class="line"></span><br><span class="line"><span class="comment">// map kernel stacks beneath the trampoline,</span></span><br><span class="line"><span class="comment">// each surrounded by invalid guard pages.</span></span><br><span class="line"><span class="meta">#<span class="meta-keyword">define</span> KSTACK(p) (TRAMPOLINE - (p)*2*PGSIZE - 3*PGSIZE)</span></span><br><span class="line"></span><br></pre></td></tr></table></figure>

<p>以上可以看见Kernel Base和phystop等等的地址分配定义。</p>

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